In order to improve the data transfer rate of a memory system, such as a dynamic random access memory (DRAM) system, people raise the clock frequency of the system. For the same purpose, the operation voltage for the memory device is reduced, too. During the read cycle of the memory system, it takes more time for the sense amplifier to catch the small signal form the array of memory cells in low operation voltage. That is a problem for the performance improving of the memory system.
Referring to FIG. 1, there is shown a timing diagram of the operation voltage of the sense amplifier of the semiconductor memory device of the prior art. In order to overcome the drawbacks of the prior art, people use a kick circuit to pull up the operation voltage of the sense amplifier of the memory device, so as to shorten the time needed for the sense amplifier to catch the small signal from the semiconductor memory device.
According to the specification, a read cycle of the semiconductor memory device comprises a period of pre-charge 13, a period of active 15, and a period of voltage kick 17, and then the signal stored in the semiconductor memory device is caught by the sense amplifier, and a read cycle is completed.
As shown in the figure, the operation voltage 12 of sense amplifier raises to a higher level during each period of voltage kick 17. If there is a sequence of read cycles, the operation voltage 12 may raise from the standard level 11 to the saturated level 19, such as VDD. After that, the voltage kick is no more helpful for the small signal sensing.
Furthermore, it would become difficult for the sense amplifier to switch to the pre-charge mode at high operation voltage. And that will take more time for the semiconductor memory device to complete a read cycle.